BiCMOS Technology and Applications by A. R. Alvarez (auth.), A. R. Alvarez (eds.)

By A. R. Alvarez (auth.), A. R. Alvarez (eds.)

The subject of bipolar suitable CMOS (BiCMOS) is an interesting one and of ever-growing functional significance. The "technology pendulum" has swung from the 2 extremes of preeminence of bipolar within the Nineteen Fifties and 60s to the plain never-ending horizons for VLSI NMOS know-how through the Seventies and 80s. but beginning within the Nineteen Eighties severallimits have been clouding the horizon for natural NMOS expertise. CMOS reemerged as a· plausible excessive density, excessive functionality know-how. equally through the mid Eighties scaled bipolar units had not just tested new excessive velocity documents, yet early types of combined bipolar/CMOS expertise have been being produced. consequently the paradigm of both excessive density . Q[ excessive pace was once metamorphasizing into a chance for either velocity and density through a BiCMOS process. Now as we method the Nineteen Nineties there were a couple of useful demonstrations of BiCMOS either for reminiscence and good judgment functions and that i count on the fad to improve over the following decade. This publication makes a well timed contribution to the sector of BiCMOS expertise and circuit improvement. The evolution is now certainly quick in order that it truly is tricky to make the sort of e-book exhaustive of present advancements. most likely both tough is the truth that the hot know-how opens a variety of novel circuit possibilities which are as but in simple terms formative of their improvement. Given those hindrances it's a herculean job to attempt to gather a e-book on BiCMOS.

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Scott, K. Fung, R. E. A. H. Shah, "An 8ns Battery Backup Submicron BiCMOS 256K ECL SRAM," Int. Solid State Circuits Conf. Dig. Tech. Papers, pp. 188 - 189, 1988. A. O. L. Bowman, "A 12ns 256K BiCMOS sRAM," Int. Solid State Circuits Conf. Dig. Tech. Papers, pp. 186 -187, 1988. 33] M. Matsui, H. Momose, Y. Urakawa, T. Maeda, A. Suzuki, N. Urakawa, K. Sato, K. Makita, J. Matsunaga, K. Ochii, "An 8ns 1Mb ECL BiCMOS SRAM," Int. Solid State Circuits Conf. Dig. Tech. Papers, pp. 38 39, 1989. V. Tran, K.

The simpler instruction set used in RISC processors imply that fast access to on- and off- chip cache is necessary. It also implies that to eliminate "wait states" faster memory is required. 38]. This speed cannot be sustained in CMOS over worst-case temperature and voltage. A number of companies are trying to adapt Bipolar technology to RISC jlPs, but the inability to integrate the required amount of on-chip memory and Bipolar's high power dissipation make this approach impractical. BiCMOS can: 1) utilize CMOS design methodologies used to design previous generations of jlPs while also providing ECL data paths as necessary, 2) integrate large fast on-chip RAM, and 3) keep power manageable by focusing it where required to optimize the speed-power tradeoff.

The encroachment of extrinsic-base dopants limits the effective area fOT collector current injection. 32]. © 1987 IEEE. 30]. This is due to a deerease in Ie as the heavily-doped extrinsie base under the emitter forms a larger pereentage of the total base area under the emitter. Careful design of the base profile at the edges of the emitter eombined with shallow emitters seem to minimize these effects. If the effeet of the extrinsie base eneroachment is studied as a function of sidewall spaeer thickness, then the impact on Ie and Is can be examined separately.

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