ARM Assembly Language Programming by Peter J Cockerell

By Peter J Cockerell

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If S is present in the instruction, and the instruction isn't one of TST, TEQ, CMP, or CMN (which are explained below), the status bits which are allowed to be altered in the current processor mode are overwritten directly by the result. ) An example should make this clear. To explicitly set the carry flag (bit 29 of R15) we might use: ORRS R15,R15,#&20000000 Now, as the second R15 is in a position, the status bits are presented as zeros to the ALU (because of the first rule described above).

During an STM, if the stack is descending, a negative offset of 4 is used. If the stack is ascending, a positive offset of 4 is used (for each register). Similarly, the difference between what the ARM does for full and empty stacks during an STM is analogous to the pre- and post-indexed addressing modes of the previous section. Consider a descending stack. An empty stack's pointer is post-decremented when an item is pushed. That is, the register to be pushed is stored at the current location, then the stack pointer is decremented (by a fixed offset of 4), ready for the next one.

However, circumstances often arise where several registers need to be saved (or loaded) at once. For example, a program might need to save the contents of R1 to R12 while these registers are used for some calculation, then load them back when the result has been obtained. The sequence: STR STR STR STR STR STR STR STR STR STR STR STR R1,[R0],#4 R2,[R0],#4 R3,[R0],#4 R4,[R0],#4 R5,[R0],#4 R6,[R0],#4 R7,[R0],#4 R8,[R0],#4 R9,[R0],#4 R10,[R0],#4 R11,[R0],#4 R12,[R0],#4 27 of 37 ARM Assembly Language Programming - Chapter 3 - The Instruction Set to save them is inefficient in terms of both space and time.

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